The present invention relates to a semiconductor device, and in particular, to a low-cost, high-speed, low-power, highly integrated semiconductor storage device (memory) and a semiconductor device integrally including a logic circuit and a semiconductor storage device.
In the recent situation of the multimedia age, such needs of high-speed data processing, lower power consumption, downsizing of devices are increasingly growing also for devices and apparatuses which are daily used by individual persons. As a technique to satisfy the needs, a large-scale integration unit including a large capacity memory and a logic circuit has attracted attention. When a memory and a logic circuit is integrally formed in one chip, the memory and the logic circuit can be connected to each other using many fine wiring zones on the chip. Therefore, a large amount of data can be transferred at a time and hence a high-speed data transfer is possible. When compared with a case in which different chips are connected to each other, the power consumed to transfer data can be reduced since the wiring capacity is small and the data transfer distance is short. Naturally, the number of chips to configure a system can also be decreased, and hence the system size can be minimized.
As a memory to be integrally included in one chip together with a logic circuit, a 6-transistor static memory cell (to be abbreviated as a 6T-static random access memory (SRAM) or a 6T-SRAM cell) including six transistors is used in general. However, there has been recently developed an example using a dynamic memory cell (to be referred to as a 1T-dynamic random access memory (DRAM) cell or a 1T-SRAM memory cell) including one transistor and one capacitor. The 1T-DRAM cell is smaller in area than the 6T-SRAM cell. Therefore, when 1T-DRAM cells are used, a larger number of memories can be integrated in unitary area of the chip. However, there exists drawbacks as follows. First, since the capacitor included in the memory cell has a three-dimensional configuration. This increases the number of processes and soars the production cost. Additionally, since data accumulated as electric charge in the capacitor decreases by a leakage current, a so-called refresh operation is required. Moreover, when compared with a case in which 6T-SRAM cells are employed, the access speed is increased, particularly, the access speed associated with an operation to change a row address. The primary reason is that the contents of storage are destructed in a read/write operation in an 1T-DRAM cell and hence the so- called re-write operation is required. The configuration and operation of a memory including 1T-DRAM cells have been well known, and hence details thereof will not be described. Reference is to be made to, for example, xe2x80x9cSuper LSI Memoryxe2x80x9d written by Kiyoo Itoh and published from Baihukan.
For a memory cell which cope with the drawbacks of the 1T-DRAM, JP-A-10-134565 describes a semiconductor storage device using a 3-transistor dynamic memory cell (to be referred to as 3T memory cell or 3T-DRAM cell herebelow). The 3T-DRAM cell occupies a less area than the 1T-DRAM occupying a less area than the 6T-SRAM. Since the 3T-DRAM cell primarily includes only transistors, it is not required to conduct the process to form a capacitor having a three-dimensional structure. Therefore, the memory including 3T-DRAM cells can be fabricated in the same transistor processes as for the memory including 6-TSRAM cells. Furthermore, according to JP-A-10-134565, when a word line is subdivided into (sub-)word lines and a logical gate is disposed for each word line, the reading and writing operations can be achieved in a non-destructive manner and the cycle time can be reduced. Consequently, when compared with the case in which 1T-DRAM cells are used, a higher-speed memory is possibly implemented.
However, even if the non-destructive operation alone is made possible, it is difficult to achieve a cycle speed similar to that of the 6T-SRAM. In the 3T-DRAM cell, charge is accumulated in the gate capacity of a transistor, the refresh operation is required. Also in this point, the 3T-DRAM cell is less easily handled as compared with the 6T-SRAM. In the 3T-DRAM cell, a fine transistor is required to keep a small memory cell area. Resultantly, it is impossible to provide a large accumulation capacity similar to that of the 1T-DRAM using a three-dimensional capacitor. Therefore, there exists a fear the refresh operation is considerably more frequently executed as compared with the 1T-DRAM cell. This increases the probability of occurrence of conflict between an access to the 3T-DRAM cell for other than the refresh operation (external access) and an internal access for the refresh operation. Additionally, when a memory and a logic circuit are mounted on one chip, a plurality of circuits access the memory in many cases. In a representative example such as graphics processing, a frame memory to store screen information must receive two kinds of accesses including read and write operations from a circuit which generates pixel information to draw an image and a read operation from a circuit which displays memory contents on a screen. To cope with a plurality of accesses as above, to completely use a memory having relatively insufficient refresh characteristic, operation becomes quite complicated.
As already described, memories employing 1T-DRAM, 3T-DRAM, and 6T-SRAM cells have been known. The 1T-DRAM cell is slow in operation, requires a high process cost, and must be refresh ed. The 3T-DRAM cell is less satisfactory in the refresh characteristic, and the 6T-SRAM cell is a drawback of large area. When using 1T-DRAM and 3T-DRAM cells requiring the refresh operation, it is difficult in operation to minimize conflicts between the refresh operation and many accesses.
In this situation, a first object of the present invention is to provide a memory capable of operating at a high speed. A second object of the present invention is to provide a memory which can be produced at a low process cost. A third object of the present invention is to provide a memory for which an external refresh operation is not required. A fifth object of the present invention is to provide a memory occupying an area which is less than an area occupied by a memory including 6T-SRAM cells. A sixth object of the present invention is to provide a memory with favorable usability for a plurality of accesses thereto.
These problems will be solved according to the present invention as follows.
To implement a high-speed memory, the read and write operations are conducted in a non-destructive operation and are pipelined. Only by conducting the read and write operations are executed in a non-destructive operation as in the prior art example, the cycle time of the memory is possibly reduced to some extent. However, by pipelining the read operation and the write operation, an external access can be received in a cycle time shorter than the inherent cycle time. In a specific configuration for the pipeline operation, a latch circuit for addresses and commands and latch circuit for data are disposed to pipeline internal operation of the memory. To implement a memory at a low process cost, a memory cell like the 3T-DRAM including only transistors is employed or a 1T-DRAM cell using a capacitor in a simple configuration such as a planar type capacitor is employed. To implement a memory for which the external refresh operation is not required, the memory is operating at a frequency higher than a frequency of an external clock signal so that the refresh operation is executed when any external access is absent. To implement a memory occupying an area which is less than an area occupied by a memory including 6T-SRAM cells, memory cells each of which includes a small number of elements such as 1T-DRAM cells or 3T-DRAM cells are employed. To implement with favorable usability for a plurality of accesses thereto, the operating frequency of the memory is set to a value more than a value obtained by adding the total frequency of external accesses to the frequency of internal access operation for the refresh operation. This makes it possible that all external accesses and the accesses necessary for the refresh operation can be executed without any conflict. That is, when viewed from all circuits to access the memory, the refresh operation can be hidden. Therefore, it is possible to implement a memory with sufficient usability.